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We present three sections for different levels of familiarity with digital IC design:
1. School of synthesis of digital circuits.
Designed for an audience of advanced schoolchildren and junior students who want to try modern technology for designing microcircuits in mass devices: synthesis from code in the Verilog hardware description language. Reconfigurable FPGAs / FPGAs are used to implement the circuits, but the same techniques apply to creating fixed ASICs, which are manufactured in the factory and become the heart of smartphones and game consoles, automotive and industrial electronics. In addition to schoolchildren and students, the section can be useful for teachers of physics and mathematics schools and heads of electronics courses who are interested in the introduction of teaching FPGAs in addition to exercises with microcontrollers and robots.
2. Microarchitecture, verification and physical design of microcircuits.
3. Advanced and experimental methods of IC design automation.
A series of talks for researchers and developers already familiar with design technologies. Covers formal verification of system-on-a-chip bus protocols from Symbiotic EDA and Gisselquist Technology, Makerchip's TL-Verilog experimental high-level pipeline design, Imagination Technologies' RVfpga package for teaching senior students to design a system-on-a-chip from Imagination Technologies, and presentations from Cadence Design Systems and Siemens EDA / Mentor Graphics, which are among the top 3 chip designer software developers.
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Section 1. School of synthesis of digital circuits.
September 14th. What a modern digital circuit is built from.
Moderator of the day: Alexander Mikhailovich Silantyev, lecturer at the National Research University “Moscow Institute of Electronic Technology” (MIET).
15.00-15.15. School opening. Why is this needed? Greetings.
Alexander Bilenko, organizer of ChipEXPO.
Yuri Panchul, design engineer and author of educational programs in the field of microelectronics.
Edmund Humenberger, President of the Austrian company Symbiotic EDA, open path specialist.
15.15-16.00. Lecture: Combinational logic and its description in the Verilog language. Theoretical material is intertwined with synthesis demonstrations for FPGAs / FPGAs in the Intel® Quartus® Prime Lite Edition environment. Alexander Mikhailovich Silantyev.
16.00-16.30. Exercise with logical elements
AND / OR / NOT / EXCLUSIVE-OR, the inputs of which are connected to the buttons, and the outputs to the LEDs of the FPGA board.
16.30-17.00. Exercise with displaying a letter on a seven-segment indicator.
17.00-17.30. Lecture: Sequential logic that introduces memory and repetition into circuits.
Alexander Mikhailovich Silantyev.
17.30-18.00. Exercise with a shift register.
18.00-19.00. Exercise for PisWords, RzRd, OMDAZZ and ZEOWAA boards with Intel FPGA Cyclone IV: Combine the shift register and output to a seven-segment letter indicator: we get an output to a multi-digit dynamic seven-segment indicator of a word (for example, student name). Exercise for a Terasic DE10-Lite board with Intel FPGA MAX10: Combine the shift register and the output of letters on a static seven-segment indicator: we get the output of a crawl line (for example, a student name).
19.00-21.00. Additional exercises and individual projects of students, with help from undergraduate and graduate students of microelectronics from participating universities: MIET, Chernigov NTU, MIREA, HSE MIEM, Innopolis and Samara University.
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September 15th.. Techniques and examples of digital design at the level of register transfers.
Moderator of the day: Sergey Anatolyevich Ivanets, Dean of the Faculty of Electronic and Information Technologies, Chernihiv National Technological University, Ukraine.
15.00-15.15. Opening of the day. What will happen after Verilog? Greetings from Steve Hoover, founder of the American startup Redwood EDA, creator of the Makerchip.com and TL-Verilog platforms.
15.00-15.15. Opening of the day. What is coming after Verilog? A greeting from Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.
15.15-15.45. Preface to an example game: a story about VGA graphics generation.
Sergey Anatolyevich Ivanets.
15.45-16.00. An exercise in drawing colorful squares and other static images on the screen.
16.00-16.30. Presentation of an example of a graphical game with parallel computed sprites and state machines for a game scenario. Demonstration of running the game on the Digilent Basys3 board with Xilinx FPGA Artix-7. Discussion of modifying the game by adding new sprites and changing the script.
Mikhail Korobkov, fpga-systems.ru.
16.30-17.00. Exercise with launching the game on PisWords, RzRd, OMDAZZ, ZEOWAA and Terasic DE10-Lite boards.
Sergey Anatolyevich Ivanets.
17.00-17.30. Preface to an example of working with sound and light: a story about the SPI and I2S protocols that are used in peripheral devices: the Digilent Pmod ALS light sensor, the Digilent Pmod MIC3 microphone and the Digilent Pmod AMP3 amplifier. Demonstration of light sensor operation. Demonstration of note recognition by measuring the period of the main harmonic sine wave. For pure sound, the period of a sine wave can be measured simply by counting the number of ticks (not musical ticks, but 50 MHz oscillator ticks on the FPGA board) between the moments when the number received from the microphone crosses a certain level. The clear sound source can be either synthetic sound from your phone, or the sound of a flute or recorder.
Semyon Moskolenko, RTU MIREA, under the leadership of Evgeny Pevtsov, Director of the Design Center and Associate Professor of RTU MIREA.
17.30-18.00. Exercises to generate a sound or sequence of sounds in response to a recognized note. The first exercise generates in response a note raised by a certain interval from the recognized one: by a tone, third, fifth or octave, depending on the position of the switches on the board. The second exercise uses a state machine to generate a major or minor triad, or a simple "Evening Bell" melody, in the key of the recognized note.
18.00-18.30. Exercise with recognizing a simple melody using a state machine and displaying the recognition result on a seven-segment indicator.
18.30-19.00. Exercise using the Digilent Pmod ENC rotary encoder to adjust the volume or pitch of the generated sound, or alternatively to change the speed of the generated melody.
19.00-21.00. Additional exercises and individual student projects on changing the game to VGA and examples of sound recognition and generation, with help from undergraduate and graduate students of microelectronics from participating universities.
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September 16th.. The first step into the architecture and microarchitecture of modern processors.
The moderator of the day is Alexander Yuryevich Romanov, Ph.D., associate professor of the Moscow Institute of Electronics and Mathematics named after V.I. A.N. Tikhonova (MIEM), National Research University Higher School of Economics (NRU HSE).
15.00-15.15. Opening of the day. RVfpga-SoC: An introduction to designing systems on a chip (SoC) using a CPU core and running RTOS Zephyr. Presentation by Zubair Kakakhel, AZKY Limited, UK representing Imagination Technologies.
Zubair was a member of the MIPS team and an experienced co-design engineer for hardware and software, with a deep understanding of the interaction between a hardware implementation and running operating systems. He defined the project and co-authored the RVfpga-SoC for the Imagination University program, which was released to educators in July 2021.
15.00-15.15. Opening of the day. RVfpga-SoC - Introduction to System-on-Chip, "SoC" Design with a real CPU core and running the Zephyr RTOS. Presented by Zubair Kakakhel of AZKY Limited, UK, on behalf of Imagination Technologies.
Zubair was a member of the MIPS team and is an experienced HW-SW Co-design Engineer, with a deep understanding of the interaction between hardware implementation and running operating systems. He defined and co-wrote RVfpga-SoC for the Imagination University Program which was released to Educators in July 2021.
15.15-16.30. Architecture: a view of a processor from a programmer's point of view. A lecture on RISC-V assembler with simultaneous instruction-level processor simulator exercises.
Nikita Polyakov is a RISC-V microprocessor designer at Syntacore, a Russian company.
16.30-18.00. Microarchitecture: a view of the processor from the point of view of circuitry. Lecture on the hardware organization of the schoolRISCV processor, with options for single-cycle and pipelined microarchitecture. Demonstration of processor synthesis and launching it on boards.
Stanislav Zhelnio, chip designer at Syntacore.
18.00-19.00. Exercise to add instructions to the processor and verify with a software test. Measuring the maximum clock frequency of the resulting processor version.
Stanislav Zhelnio.
19.00-21.00. Additional exercises and individual projects for students to change the processor and integrate it with peripheral devices. With help from undergraduate and graduate students of microelectronics from participating universities.
Section 2. Seminar "Microarchitecture, verification and physical design of microcircuits"
September 14th.
11: 00-11.05. Opening. Greetings from Alexander Bilenko, ChipEXPO organizer.
11.05-11.15. Why is this needed? Review of the topics of the reports of the day.
Yuri Panchul, microcircuit design engineer (CPU, GPU, Networking) and author of educational programs in the field of microelectronics.
11.15-11.50. What is going on in the global community of open path designers for microcircuits?
Edmund Humenberger, President of the Austrian company Symbiotic EDA.
# Design routes.
11.15-11.50. The state of the open source chip design union.
Edmund Humenberger, CEO and co-founder of Symbiotic EDA (Austria), an evangelist of the open design flows.
# Design flows.
12: 00-12: 35. How to pipe a data stream with maximum throughput, minimum memory, and without excessive latency: double buffers, queues, and credit counters.
Dmitry Smekhov, FPGA development engineer, IRQ, InSys and Inline Group.
Roman Voronov, Innopolis University, under the direction of Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# General microarchitecture.
12: 45-13: 20. Methodology for the dedicated implementation of end-to-end control mechanisms for the computational process in hardware microarchitectures.
Alexander Antonov, Associate Professor, Ph.D., ITMO University.
# Design routes.
13: 30-14: 05. Variety of implementations of FIFO queues: a trade-off between the number of writes and reads in one cycle, the number of ports and memory technology, bandwidth and power consumption.
Sergey Anatolyevich Ivanets, Dean of the Faculty of Electronic and Information Technologies, Chernihiv National Technological University.
# General microarchitecture.
14: 15-14.50. Using open design paths Qflow and OpenLANE to measure the physical performance of educational and research projects in microarchitecture.
Mikhail Mikhailovich Chupilko, Senior Researcher, Ph.D. Institute for System Programming. V.P. Ivannikov Russian Academy of Sciences.
Vladislav Safonov, Innopolis University, led by Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# Design routes.
15: 00-15: 35. A variety of arbiters and their applications for access sharing and dynamic memory allocation. Round-robin algorithms, with fixed or programmable priorities. Special arbiters with multiple grants and static memory state storage.
Konstantin Buttercup, Innopolis University, under the leadership of Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# General microarchitecture.
15: 45-16.20. Verification not only for verifiers, part 1: the use of the temporal logic language SystemVerilog Assertions by the developer of the RTL block to improve quality, control the coverage of special cases and document functionality.
Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
Yaroslav Kolbasov, Senior Integrated Circuit Verification Engineer, Elvis Research and Development Center.
# General verification.
16: 30-17: 05. Introduction to caches: microarchitecture and verification - Andrey
Vorotnikov, Lead Engineer KM211.
17: 15-17: 50. Replacement Algorithms in Multisection Caches: When
apply exact LRU (Least Recently Used), and when - approximate.
Nikolay Ternovoy, Syntacore engineer.
# Microarchitecture and processor verification.
18: 00-18: 35. On the border with the outside world: reset, bounce and synchronization of input in electronic circuits.
Mikhail Korobkov, FPGA-Systems.ru.
# RTL receptions.
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September 15th.
11.00-11.15. Opening of the day. The Minsk office of SK Hynix is an example of international cooperation in microelectronics.
11.15-11.50. TL-Verilog's high-level methodology makes conveyor design easier and more reliable.
Steve Hoover, founder of the American startup Redwood EDA, creator of the Makerchip.com and TL-Verilog platforms.
# Design routes.
11.15-11.50. A high-level TL-Verilog methodology allows designing a pipeline easier and with fewer bugs.
Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.
# Design flows.
12: 00-12.35. Creation of multi-port memory from several single-port ones: the optimal number of banks and minimization of conflicts using the read and write scheduler.
Artem Voronov, Roman Voronov, Innopolis University, under the direction of Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# General microarchitecture.
12: 45-13: 20. Elements of SystemVerilog that every verifier should know when writing drivers and tests: three types of delays, complex data structures, queues and associative arrays, threads and their synchronization, DPI and its applications.
Sergey Anatolyevich Ivanets, Dean of the Faculty of Electronic and Information Technologies, Chernihiv National Technological University.
# General verification.
13: 30-14: 05. Restoring the order of transactions after processing them by a block with variable latency and out-of-order responses.
Nikita Polyakov, senior engineer at Syntacore.
# General microarchitecture.
14: 15-14: 50. FPGA licensed as soft IP for embedding in ASIC, using the example of Menta eFPGA.
Alexey Vorotnikov, Head of the Department of Verification and Rototyping of KM211 End Devices
# Design routes.
15: 00-15: 35. You can work with linked lists without a processor: the microarchitecture of the hardware unit for working with dynamic structures in memory.
Alexander Demidenko, VMK Moscow State University, under the leadership of Mikhail Sergeevich Shupletsov, Associate Professor of the Department of Mathematical Cybernetics, Ph.D.
# General microarchitecture.
15: 45-16.20. Verification is not just for verifiers, part 2: the RTL developer uses functional coverage groups in SystemVerilog to verify the completeness of the test suite, document functionality, and improve quality through formal verification.
Ilya Kudryavtsev, Dean of Samara University
# General verification.
16: 30-17: 05. Memory consistency models: specification, implementation and verification.
Alexander Kamkin, Leading Researcher, Candidate of Physical and Mathematical Sciences, Institute for System Programming. V.P. Ivannikov RAS
# Microarchitecture and processor verification.
17: 15-18.50. Coherent cache memory for multicore processors: simulation and verification.
Anton Garashchenko, engineer of JSC SPC ELVIS.
# Microarchitecture and processor verification.
18: 00-18.25. Techniques for measuring and optimizing the dynamic power consumption of microcircuits when designing at the level of register transfers.
Alexander Mikhailovich Silantyev, MIET.
# RTL receptions.
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September 16th.
11.00-11.15. Opening and review of topics of the reports of the day.
Yuri Panchul, design engineer and author of educational programs in the field of microelectronics.
11: 15-11: 50. Introducing "IUP" - The Imagination University Program. This program includes the use of a fully verified open source industrial processor core and RISC-V architecture to teach computer architecture and system-on-a-chip (SoC) design.
Robert Owen. Principal Consultant: World University Program, Imagination Technologies, UK.
The IUP provides best-in-class undergraduate and postgraduate materials in Computer Science, Computer and Electronic Engineering on the topics of Mobil Graphics, Computer Architecture, and SoC Design. A new course on EdgeAI principles and practices (end of issue '21) is currently in development. Robert Owen has been working in this field since 1994 and is known in Russia for Texas Instruments university programs in the field of DSP, and then for MIPSfpga and Connected MCU Lab.
# Microarchitecture and processor verification.
11: 15-11: 50. Introducing the "IUP" - The Imagination University Program - including using an open-source fully-verified industrial processor core with RISC-V architecture to teach Computer Architecture and System-on-Chip (SoC) design.
Robert Owen. Principal Consultant: Worldwide University Program, Imagination Technologies, UK.
The IUP provides best-in-class materials for under-graduate and post-grad education in Computer Science, Computer and Electronic Engineering on the topics of Mobil Graphics, Computer Architecture and SoC Design.
In development currently is a new course about EdgeAI its principles and practices (release end'21).
Robert Owen has been working in this field since 1994 and is known in Russia for the Texas Instruments' DSP University Program, and then subsequently for the MIPSfpga and Connected MCU Lab activities.
# Processor microarchitecture and verification
12: 00-12.35. Techniques for designing and verifying interfaces for processing data streams based on the AXI Stream protocol.
Maxim Latypov, Andrey Starodumov, Innopolis University, under the leadership of Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# Processing data streams.
12: 45-13.20. Functional verification on SystemVerilog: using a language of interconnected constraints on pseudo-random transactions fields to generate interesting digital circuit testing scenarios.
Yaroslav Kolbasov, Senior Integrated Circuit Verification Engineer, Elvis Research and Development Center.
# General verification.
13: 30-14: 05. A practical example of functional verification on SystemVerilog: we find flaws in the example of the AXI module from Xilinx, using pseudo-random testing, functional coverage, and the SVA temporal logic assertion language.
Ilya Kudryavtsev, Dean of the Samara University.
# General verification.
14: 15-14: 50. Design and verification of module connection blocks in a system-on-chip using AXI Lite and AXI Stream protocols.
Stanislav Zhelnio, Syntacore Engineer.
# Processing data streams.
15: 00-15: 35. An overview of the microarchitecture of systolic arrays for accelerating machine learning computations and examples of implementation.
Alexander Yurievich Romanov, Associate Professor, Ph.D., MIEM, National Research University Higher School of Economics, his students and postgraduates.
Sergey Pasynkov, Innopolis University, under the leadership of Rafael Ilyasov, Chief Electronics Engineer of the Innopolis University Design Center.
# Hardware accelerated machine learning.
15: 45-16: 20. What is the Universal UVM Verification Methodology and the limits of its applicability.
Yaroslav Kolbasov, Senior Integrated Circuit Verification Engineer, Elvis Research and Development Center.
Ilya Kudryavtsev, Dean of the Samara University.
# General verification.
16: 30-17: 05. RISC-V processor verification.
Evgeny Primakov, lecturer at MIET.
# Microarchitecture and processor verification.
17: 15-17: 50. Increase the productivity of the verifier engineer through the use of portable tests in C / C ++ at all stages of development: from autonomous verification of a block, subsystem, system-on-chip and prototyping to a finished integrated circuit.
Fyodor Mikhailovich Putrya, Head of the Verification Department, JSC SPC ELVIS.
# Microarchitecture and processor verification.
18: 00-18: 35. Research Grant Programs in Microelectronic Design.
Alexander Mikhailovich Silantyev, lecturer at MIET.
# Research funding.
18: 45-19.00. Closing speech Alexander Bilenko, organizer of the ChipEXPO conference.
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Section 3. Advanced and experimental methods of microcircuit design automation.
September 14th.
11: 00-11.05. (General report with section 2) Opening. Greetings from Alexander Bilenko, ChipEXPO organizer.
11.05-11.15. (General report with section 2) Why is it necessary? Review of the topics of the reports of the day.
Yuri Panchul, microcircuit design engineer (CPU, GPU, Networking) and author of educational programs in the field of microelectronics.
11.15-11.50. (General report with section 2) What is happening in the global community of creators of open paths for designing microcircuits?
Edmund Humenberger, President of the Austrian company Symbiotic EDA.
# Design routes.
11.15-11.50. The state of the open source chip design union.
Edmund Humenberger, CEO and co-founder of Symbiotic EDA (Austria), an evangelist of the open design flows.
# Design flows.
12.00-13.20. Formal verification of the system-on-chip components with
the AXI interface.
Submitted by Dr. Dan Gisselquist of Zipcpu.com / Gisselquist
Technology, USA.
# Design routes.
# Processing data streams.
Dr. Dan Gisselquist - Owner and Founder of Gisselquist
Technology, LLC, which deals with point contracts for
digital electronics design and formal circuit verification.
Dan is best known today as the author of the ZipCPU blog and consultant on
formal methods. Dr. Gisselqvist has a master's degree in
Computer Engineering and Doctorate in Electronic Engineering from
Air Force Institute of Technology.
12.00-13.20. Formal verification of the AXI bus interface logic
connecting the system-on-chip (SoC) components.
Presented by Dr. Dan Gisselquist from Zipcpu.com / Gisselquist
Technology, USA.
# Design flows.
# Data stream processing.
Dr. Dan Gisselquist is the owner and founder of Gisselquist Technology,
LLC, a services based microbusiness focused digital electronic design
and formal verification. He is best known today as the author of the
ZipCPU blog, and for its focus on formal methods. Dr. Gisselquist has an
M.D. in Computer Engineering and a Ph.D. in Electrical Engineering from
the US Air Force Institute of Technology.
13.30-14.05. Template for creating a verification environment on SystemVerilog with low overhead costs.
Dmitry Smekhov, FPGA development engineer, IRQ, InSys and Inline Group.
# General verification.
14.15-14.50. Questa Advanced Simulator: Advanced debugging and verification techniques increase engineer productivity.
Presentation from Siemens EDA.
# Design routes.
14.15-14.50. Questa Advanced Simulator: The advanced debugging and verification techniques increase engineer productivity.
A presentation from Siemens EDA.
# Design flows.
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September 15th.
11.00-11.15. (General report with section 2) Opening of the day. The Minsk office of SK Hynix is an example of international cooperation in microelectronics.
11.15-11.50. (General presentation with section 2) The high-level methodology of TL-Verilog makes it easier and more reliable to design a conveyor.
Steve Hoover, founder of the American startup Redwood EDA, creator of the Makerchip.com and TL-Verilog platforms.
# Design routes.
11.15-11.50. A high-level TL-Verilog methodology allows designing a pipeline easier and with fewer bugs.
Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.
# Design flows.
12.00-12.35. Memory compilers for designing ASIC microcircuits: building logical memories with specified parameters from physical ones, with optimization of latency and power consumption.
Alexander Mikhailovich Silantyev, MIET, together with Alfa-Chip.
# Design routes.
12.45-13.20. How Cadence software helps the developer optimize designs to minimize power consumption.
Alexey Ivanov, Lead Program Manager, Cadence Design Systems.
# Design routes.
13.30-14.05. Experience in creating and using our own Verification IP in the SK Hynix branch in Minsk, Belarus.
# General verification.
14.15-14.50. From idea to sending to the factory: programs and hardware accelerators for automating various stages of microcircuit design from Siemens EDA.
Presentation from Siemens EDA.
# Design routes.
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September 16th.
11.00-11.15. (General report with section 2) Opening and review of the topics of the reports of the day.
Yuri Panchul, design engineer and author of educational programs in the field of microelectronics.
11: 15-11: 50. Introducing "IUP" - The Imagination University Program. This program includes the use of a fully verified open source industrial processor core and RISC-V architecture to teach computer architecture and system-on-a-chip (SoC) design.
Robert Owen. Principal Consultant: World University Program, Imagination Technologies, UK.
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